The feedback path contains a divide by 2 circuit $(N=2)$. Let's use the VCO with the characteristics
$$
K_{V C O}=1.57 \times 10^9 \mathrm{radians} / V \cdot s
$$


The gain of the phase detector (knowing $V D D$ is 1 V ) is

$$
K_{P D t r i}=\frac{1}{4 \pi}
$$


The lock range, $\Delta f_{\mathrm{L}}$ will be set to 20 MHz . Again let's set $\zeta=1$. 
$$
\Delta \omega_L=4 \pi \zeta \omega_n \rightarrow \omega_n=10 \times 10^6 \mathrm{radians} / \mathrm{V} \cdot \mathrm{~s}
$$


$$
R_2 C=200 \mathrm{~ns}
$$


Let's set the capacitor to 10 pF and $R_2$ to 20k. Solving $R_1$ gives $42.5 \mathrm{k}\left(=R_1\right)$.

The simulation results are seen. We should first notice that the VCO's control voltage doesn't have the excessive ripple like we had in the DPLL using the XOR gate phase detector. The response of the loop shows a nice $\zeta=1$ shape. Again note that a DPLL loop's pull-in range is limited by the VCO's operating frequency (which, in this example uses the VCO, the ranges from 50 to 150 MHz ). A good exercise to perform at this point is to change the divider in the feedback path (to divide by $1,2,4$, etc.) and the input frequency (a signal we've called data) and look at the robustness of the loop.